HOST-2012  
IEEE International Symposium on HARDWARE-ORIENTED SECURITY and TRUST
June 3-4, 2012, Moscone Center, San Francisco, CA
Held in conjunction with DAC-2012  (http://www.hostsymposium.org)

Call for Papers

A wide range of applications, from secure RFID tagging to high-end
trusted computing, relies on dedicated and trusted hardware
platforms. The security and trustworthiness of such hardware designs
are critical to their successful deployment and operation. Recent
advances in tampering and reverse engineering show that important
challenges lie ahead. For example, secure electronic designs may be
affected by malicious circuits, Trojans that alter system
operation. Furthermore, dedicated secure hardware implementations are
susceptible to novel forms of attack that exploit side-channel leakage
and faults. Third, the globalized, horizontal semiconductor business
model raises concerns of trust and intellectual-property
protection. HOST 2012 is a forum for novel solutions to address these
challenges. Innovative test mechanisms may reveal Trojans in a design
before they are able to do harm. Implementation attacks may be
thwarted using side-channel resistant design or fault-tolerant
designs. New security-aware design tools can assist a designer in
implementing critical and trusted functionality, quickly and
efficiently.

The IEEE International Symposium on Hardware Oriented Security and
Trust seeks original contributions in the area of hardware-oriented
security. This includes tools, design methods, architectures, and
circuits. In addition, novel applications of secure hardware are
especially welcome. HOST 2012 seeks contributions based on, but not
limited to, the following topics.

 -      Trojan detection and isolation
 -      Implementation attacks and countermeasures
 -      Side channel analysis and fault analysis
 -      Intellectual property protection and metering
 -      Tools and methodologies for secure hardware design
 -      Hardware architectures for cryptography
 -      Hardware security primitives: PUFs and TRNGs
 -      Applications of secure hardware
 -      Interaction of secure hardware and software

To present at the symposium, submit an Acrobat (PDF) version of your
paper on the symposium submission website. The page limit is 6 pages,
double column, IEEE format, with a minimum font size of 10
points. Submissions must be anonymous and must not identify the
submitting authors, directly or indirectly, anywhere in the
manuscript.

SCHEDULE:
        Submission of Paper:         January 20, 2012   
        Notification of Acceptance:  March 23, 2012
        Camera Ready Paper:          April 13, 2012